This is the laboratory notebook of Damon Bruccoleri. Here you will find engrossing, thoughtful and fun commentary/opinion. Leave a comment and let others know what you think about any post here, view my photo gallery, or sign my guestbook. MY FAVORITE ALBERT EINSTEIN QUOTES:
"...one of the strongest motives that lead men to art and science is escape from everyday life with its painful crudity and hopeless dreariness, from the fetters of one's own evershifting desires. A finely tempered nature longs to escape from the personal life into the world of objective perception and thought."  Albert Einstein




Tuesday, January 21, 2014 
Interesting Circuit Problem 

A couple months ago I ran across a circuitry problem that may interest those with a little electronics knowledge. We were getting failures on a high percentage of new product, but not on all of them. The product was warning that its internal 15v supply was out of tolerance (and faulting). A manual check with a voltmeter showed the 15v supply was within the required +/10% tolerance. Other internal supplies were monitored as well by the computer and they never exhibited this issue. Below is a schematic of the components involved, what I found and the interesting solution.
What this schematic is showing is three resistor divider circuits that divide down the +15, +5v and the 15 volt supplies to feed the A/D converter inputs (there is some additional filtering and protection not shown). This A/D converter can resolve a range of 0v to +3v signal thus the need to divide down the voltages before conversion. Additionally the 15v rail voltage is "translated" to a positive voltage by raising it with the +5V. The code in the computer then reads the A/D converter and looks to see if the value read is out of +/10% tolerance.
There is a problem though with the 15v divider circuit. Do you see it? The 15v circuit is dependent on the +5v voltage as well. So for instance if the +5v rail is 8% too high (within spec), and the 15v signal is 8% too low (also within spec), the resulting divided/translated voltage may be more than 10% out of whack (this is a highly technical term). The unit would then erroneously fault.
I found a simple software change that put this issue to rest. We need to first read the +5 rail voltage. Then the 15v rail voltage is read and we subtract out the component of +5v rail voltage from the 15v reading. To do this requires some math and Kirchoff's voltage law.
V_{AD3} = V_{+5v}  ( V_{+5v}  V_{15v}) R_{5} /( R_{5} + R_{6})
Next we have to solve for V_{15v} :
V_{15v} = (V_{+5v}  V_{AD3})(R_{5} + R_{6})/R_{5} + V_{+5v}
I implemented this equation in the firmware of the computer and it worked like a charm! I implemented it, but did not consider this solution to be optimal. In subsequent designs I made sure we did not use the +5v supply to translate the 15v supply voltage, but for this product this software solution had several benefits:
 Easy fix for units already in field. No recall.
 No waste for already manufactured inventory. We can use existing stuffed pcb's.
 We did not need to delay an already delayed product.
 No additional cost for the pcb NRE.
There were some other issues with this solution, scaling issues and floating point issues, but those are for another lab note.
Did you know you can get all of my older lab notes by hitting the archive button on my top banner or to the left?

damon at 3:28 AM 
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Saturday, January 11, 2014 
Redundant processing systems 

I would like to expound more on Byzantine Systems and redundancy in general. The first type of system I would like to present is a dual architecture. This system is not actually redundant. It is a crosschecking architecture. In this system 2 processor cross check each other. If either one fails, a system fail is declared. This system has no way of determining which processor is at fault. Both get shut down. A fault causes a system fail or shut down. System reliability decreases in this architecture since if either fail, the system fails. What improves is system integrity, where integrity is defined as the lack of invalid system state. In this system, and the following systems, the system is assumed to be deterministic. Determinism loosely means the processors have identical inputs, clocks... Note in this system the output of one of the processors is actually used. The other processors output is simply used for crosscheck.
The next type of system is a voting system. A basic voting system has three processors and the system is deterministic. In this type of a system both reliability and integrity are increased. The weak point of this system is the voter. There are several proposals for systems with multiple voters. This type of system requires at least 3 processors to break the tie vote. Systems with more processors have been researched and implemented, but of course with increased cost. It's interesting to note that in the SpaceX rocket program the architecture they chose was a modular 3 redundant system (such as this) with 3 processors which are crosschecked (by 3 more processors as in the previous example.)
The final type of system is the Byzantine system. Byzantine Systems lend themselves to implementation as distributed nodes. A basic goal of a Byzantine system is to keep all healthy nodes in agreement. This is the same thing as saying that Byzantine agreement keeps the system deterministic. This type of system requires at least 4 processors to tolerate 1 failure. To tolerate multiple failures even more than 4 processors are required. The exact number of redundant processor is = number of failures *3 + 1. A Byzantine system eliminates the voter. Each processor implements its own voting function. The figure to the left illustrates the basic problem of why this system will not work with less than 4 processors. Here we see a faulty node 1 (in Byzantine terms we use the word malicious rather than faulty) giving different outputs to two different distributed nodes. When a new command is propagated in this system there are several rounds
of transmissions between the processors to keep nodes in agreement of
the command. In this example nodes 2 and 3 cannot agree. Neither node 2 or 3 can tell if Node 1 is the faulty node, or the other node is faulty. There is a need for a fourth node to cast a tiebreaking vote. The protocol is lengthy and costly in terms of communications bandwidth. It does however provide the highest level of reliability.
Relaxed restrictions on the Byzantine network are the object of research and several new protocols have been proposed that are less costly ( for example Khosravi & Kavian, 2012).

damon at 8:21 AM 
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Thursday, December 05, 2013 
Why is Nyquist important to A/D converters? 

To minimize aliasing an antialiasing filter is needed before an A/D converter. How do you design this prefilter? What is this aliasing?
Shannon, and Nyquist later, said that the maximum signal we can reconstruct is half of the sampling rate. If the signal we sample has components higher than 1/2 sampling rate then we get a phenomena called 'aliasing.' If I were to send an aliased signal back out of a computer to a D/A converter it would look like the signal was 'shifted' in frequency. This frequency shift would be equal to the sampling rate. Suppose a signal of Fs was put into an A/D converter and the sampling rate was Fs. It might appear on a D/A converter as a DC signal (because Fs  Fs = 0 ).
As an everyday example of aliasing, have you ever seen a moving fan appear still under a strobe light? When the strobe is blinking at the same rpm's as the fans rotational speed, the fan will appear motionless.
The aliasing phenomena can occur if the sampled signal is at or above 1/2 the sampling rate OR IF IT HAS (Fourier) COMPONENTS AT OR ABOVE THIS RATE. In this case just those components above the Nyquist rate would be aliased, but the total signal, if reconstructed, will be distorted.
How do we deal with this issue? Typically we use an antialiasing filter on the front end of the A/D. It might be as simple as an RC or more complicated as a multipole active filter in a Chebychev or Butterworth configuration.
The key is to understand how much attenuation we need at the stop band. Suppose our A/D is 12 bits. The ideal SNR is 72dB (= 20* log(4096)). Our filter should be designed to provide 72 db of attenuation at the stop band.

damon at 8:29 PM 
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Wednesday, September 25, 2013 
Byzantine Fault Tolerance 

Where did the term 'Byzantine' in Byzantine Failure originate?
Why not something else?" The term comes from the Byzantine
Generals Problem. This is a generalization of the Two Army Problem. See my previous post. The Byzantine Generals are a metaphor for nodes of a distributed system.
The Byzantine Generals are introduced in a research paper by Leslie
Lamport, Robert Shostak, and Marshall Pease (1982), The Byzantine Generals Problems.
In this paper the authors imagine an encampment of a large enemy
army. Surrounding this encampment are the Byzantine
Generals. Each general commands a small brigade of soldiers.
Individually the Generals would lose to the enemy, but united they
win. The objective is for the Byzantine Generals to mount a
coordinated attack. Unfortunately, things are gummed up a
bit. It's a historical fact the Byzantine army had significant
treachery in its high ranks. A general may be malicious and
working for the other side. This would be considered a "Byzantine
Failure" of a node in this distributed system. The objective then
becomes for the system as a whole to act in concert in the presence of
these Byzantine Failures. A general
solution to this problem can be quite difficult. Consider for
example a malicious general tells half of the other generals to attack,
and the other half to retreat. What protocol can healthy nodes use to
maintain agreement? What if there are more than 1 malicious
general in the system acting in concert? Given we have an
algorithm that maintains 'interactive consistency' what is the maximum
number of malicious generals that the distributed system can
tolerate? Interactive consistency loosely means that all
nonmalicious generals (healthy nodes) always agree.

damon at 6:04 PM 
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Wednesday, September 25, 2013 
The exponential (IIR) digital filter 

In
the last lab note we looked at the boxcar filter structure. That
was an example of an FIR filter. The exponential filter is an IIR
filter. In a simple implementation of this filter we
calculate the filter output by taking the current sample, adding it
to the previous output then dividing by 2. Mathematically y=½(x+yz^{1}). Since the output is a function of the previous output this is an Infinite Impulse Response filter, or IIR filter.
One
of the concerns about IIR filters is that an impulse or perturbation on
the input will ring forever on the output. This may be true
if we are talking about real math. In a typical embedded system we
work with a fixed point math. Notice that in our equation the
impulse is cut in half each sample time. So for instance, our
samples may be from a 12 bit A/D converter. After 12 sample times
our impulse gets cut in half 12 times and then would disappear. In
this case it will not ring forever. On the other hand a fixed
point math can cause other issues on filters with more interesting
pole/zero placement, but we are good here.
For the above function H(z) = Y/X = 1/(2z^{1}).=
z/(2z1) There is a zero at 0 and a single pole at
z=1/2. This is within the unit circle, thus the filter is
stable. To plot the frequency response we set z=e^{jωT }. Then we normalize by setting T=1. We can use Wolfram Alpha to plot the equation H(ω) = 1/(2e^{jω}). And I copied the plot here for convenience.
Here
the horizontal axis is in Hz. This filter is down to 0.7 at a
frequency of 0.14Hz (remember this equation is normalized to a
sampling frequency of 1 Hz).
If this is too much filtering, or
too little filtering you can try adjusting the weighting of the two
terms in the exponential filter. For instance, what if you choose
the weighting y = ¼ (3x + yz^{2})? Here I tried to use a
mod 2 divisor to make the math dead nuts simple to implement on a fixed
point processor. On an FPGA you would not even need to divide or
shift, just pick off the right bits!! All we need is two 'add'
operations. Can you calculate the frequency domain function and
plot it?
If you have any other common filter topologies, leave a comment for future discussion. 
damon at 5:55 PM 
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Wednesday, September 25, 2013 
In embedded systems it is quite common
to need a little bit of filtering on analog quantities. Programmers
sometimes feel they need the filtering to help smooth any analog
conversion noise. Two type of filters commonly used are the Boxcar and
the Exponential filter. Both are simple to implement. Its important to
understand the impact these filters have on delay and frequency
response, and to evaluate their comparative effectiveness.
The
Boxcar filter is a simple averaging filter. Technically it is an FIR
filter. Typically you would obtain your next analog value, add it to the
last n1 values read, then divide by n. It's just a simple average of
the last few values read.
A common value for n is 4. The Z transform of a filter with n=4 is H(z) = ¼ (z^{3}+z^{2}+z+1)/(z^{3})
. There are three poles at the origin in the Z domain. Thus this filter
is stable. There is one real zero at 1, and two complex conjugate
zero's at +i and i. The (normalized) frequency response is given by H(e^{j}^{ω}) = magnitude(¼ + ¼e^{j}^{ω}+ ¼e^{j2}^{ω}+¼e^{j3ω}). We can use WolframAlpha to plot this function.
Click the link to plot the function. In the following image (copied from Wolfram) we see
several cycles of normalized frequency response including mirroring above
half the sample rate.
Note
that the horizontal axis is in Hz. The sampling frequency ia 1Hz. One
half the sample rate ia 0.5Hz  the Nyquist rate). What you are seeing
above 0.5Hz is a periodic mirror of the response. But focus on the response below 0.5 Hz. How UGLY!
Lets try to
plot the response for n=2. With this filter all we do is add the current
and previous samples and divide by 2. The characteristic equation is Y
= ½(X + Xz^{1}) .& The transfer function is H(z) = ½(1+z^{1}) = ½(1+z)/z . This has a single pole at 0 and a zero at 1. Thus its stable. The normalized frequency domain function H(e^{jω}) = ½(1+e^{jω}). Its normalized for a sample time of 1sec. The plot looks like this. This looks more well behaved!
Note
that the horizontal axis this time is in Hz. Since the sample time is a
normalized 1second, then the sample frequency is 1.0 Hz, and the
Nyquist frequency is 0.5 Hz.
In my next Laboratory Note we will look at the Exponential Filter. This is actually my favorite and I will show you why! 
damon at 5:52 PM 
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Tuesday, June 26, 2012 
A software concern that I recently investigated was Undo/Redo. An OOP programmer tries to use design patterns as a tool for recognizing software patterns that repeat themselves from project to project. As an engineer or programmer we all come to recognize these recurring design patterns. These patterns are abstract. They help us to see seemingly different projects as having common threads. Once we recognize them they help us to do our job quicker and possibly more thoroughly.
There are two design patterns I looked at for implementing an Undo/Redo facility for a software project. Both require an Undo stack and a Redo stack. As the user executes commands in the target program the commands are put on the Undo stack. If the user undoes an operation, that operation is then put on the redo stack.
The first method I investigated was to use something like the command pattern to create a central mechanism for each user operation. The problem is that each command would need its opposite command for the undo operation. Not many operations are reversible. This would mean the operations presented to the user would necessarily be limited to reversible operations.
The second method, the method I chose to implement, was to save the state of the software at each step. A design pattern that can implement this functionality is the Memento design pattern.
The Undo/Redo software concern can be demonstrated to be a crosscutting concern. That is this concern is highly coupled with the other aspects of the target program. As such I additionally demonstrated an Aspect Oriented (AOP) approach to modularization of this concern.
Link to report 
damon at 8:35 PM 
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Monday, April 16, 2012 


Tuesday, December 27, 2011 


Thursday, December 15, 2011 
Sine Oscillation Generating Method Comparison Chart 

Found out two interesting item's. First, there does not seem to be a simple IC for generating sine waves. Second, I found this interesting chart. Use it as a starting point for your design. Its from Texas Instruments App Note 263 "Sine Wave Generation Techniques". Click on it for a larger view.

damon at 11:30 PM 
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